Telecommute Lead Static Timing Analysis Engineer in San Jose

Job ID: Available for Members

Location: California

Compensation: Salary

Posted: Friday, March 30, 2018

Job Category: Engineering, Information Technology

Telecommute Level: 100% Telecommute

Travel Requirements: No Travel

Weekly Hours: Full Time

Employment Status: Permanent

Employer Type: Employer

Career Level: Experienced

Education Level: Bachelors

Additional Information: Benefits Available

Job Summary

A software firm is filling a position for a Telecommute Lead Static Timing Analysis Engineer in San Jose.

Core Responsibilities Include:

  • Running static timing analysis on large complex SoCs
  • Developing constraints including modeling clock domain crossings
  • Analyzing STA results and enhance/modify timing constraints

Position Requirements Include:

  • 7+ years of STA experience Cadence Tempus or ETS (Encounter Timing System)
  • Understanding of MMMC timing in the FinFET nodes (14nm, 7 nm) using Multi VT libraries
  • Excellent understanding of constraint generation
  • BSEE