Consulting Engineer 3

Job Summary

To support the development of next-generation network devices, the contract Consulting Engineer 3 will design and implement advanced Design-for-Test (DFT) features, ensuring high-quality and manufacturable silicon designs while working remotely on a contract basis for 12+ months.

Key Responsibilities

• Implement hardware Design-for-Test (DFT) features including scan, Memory BIST, Built-In Self-Test, and boundary scan
• Set up and debug DFT simulations, providing essential support for post-silicon testing and debug
• Collaborate with multi-functional teams to develop innovative DFT Intellectual Property (IP) and integrate testability features at the RTL level

Required Qualifications

• Bachelor's or Master's Degree in Electrical or Computer Engineering with 8-10 years of relevant ASIC DFT experience
• Proficient in JTAG protocols, Scan and BIST architectures, and integrating third-party IPs
• Experience with ATPG and EDA tools such as Tessent, Xcelium, Genus, and Tempus/Primetime
• Hands-on experience with post-silicon debug of DFT patterns and successful production release
• Ability to work independently and debug complex issues with minimal mentorship