Design Verification Engineer

Job Summary

A company is looking for a Design Verification Engineer.

Key Responsibilities

• Write test bench code, primarily in SystemVerilog with UVM methodology
• Debug waveform/log issues using simulators or waveform viewers
• Review coverage data, collaborate with designers, and collect updates

Required Qualifications

• 8-12 years of experience in hardware design verification
• Extensive experience with Universal Verification Methodology (UVM)
• Proficient in SystemVerilog for writing test benches and verification logic
• Understanding of networking protocols including TCP/IP and packet processing
• Bachelor's degree preferred