Design Verification Engineer

Job Summary

Working remotely during PST hours, the contract Design Verification Engineer will ensure the functional correctness and performance of complex silicon designs by developing UVM-based verification environments and executing comprehensive test plans.

Key responsibilities:

• Develop UVM-based verification environments including agents, scoreboards, and monitors
• Create and execute test plans at block, subsystem, and chip levels
• Collaborate with RTL, DFT, and design teams for debug and validation

Required qualifications:

• 3+ years of ASIC/SoC verification experience
• Strong knowledge of SystemVerilog and UVM
• Experience with VCS/Questa/Xcelium simulators
• Familiarity with coverage-driven verification methodology
• Proficiency in scripting languages such as Python, TCL, or Perl