DFT Lead

Job Summary

To support a growing team, the contract DFT (Design for Test) Lead will implement Hardware Design-for-Test features, develop innovative DFT IP, and participate in the creation of hardware DFT strategies while working remotely.

Key responsibilities:

• Implement Hardware Design-for-Test features such as scan, mbist, BISR, and boundary scan, while setting up and debugging DFT simulations
• Develop innovative DFT IP in collaboration with multi-functional teams, ensuring full chip design integration with testability features
• Participate in the creation of hardware DFT and physical design aspects for new silicon device models, driving reusable test and debug strategies

Required qualifications:

• Bachelor's or Master's Degree in Electrical or Computer Engineering with 8-10 years of experience
• Experience with JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan
• Familiarity with ATPG and EDA tools like Tessent, Xcelium, Genus, and Tempus/Primetime
• Hands-on experience with post-silicon debug of DFT patterns and releasing to production