Lead ASIC DFT Engineer

Job Summary

Leading the end-to-end Design-for-Test strategy, the remote Lead ASIC DFT Engineer will implement and debug complex ASIC/SoC designs while ensuring effective test coverage and DFT best practices.

Key responsibilities:

• Define and implement scan, ATPG, MBIST, LBIST, and JTAG architectures
• Lead DFT insertion, verification, and sign-off processes
• Drive test coverage, diagnosis, and silicon debug efforts

Required qualifications:

• 10+ years of ASIC DFT experience
• Strong expertise in scan, ATPG, MBIST, LBIST, and JTAG
• Experience with Synopsys, Cadence, or Siemens Tessent tools
• Proficient in SoC, RTL, and silicon validation
• Expertise in debugging, fault coverage, and test methodology