Lead ASIC DFT Engineer

Job Summary

Owning end-to-end Design-for-Test activities, the 100% remote Lead ASIC DFT Engineer will manage DFT architecture, scan implementation, ATPG, and MBIST/LBIST integration while collaborating with various teams to ensure high test coverage and silicon quality.

Key responsibilities

• Own DFT architecture, implementation, and sign-off for ASIC/SoC designs
• Drive ATPG setup, pattern generation, simulation, and coverage closure
• Support post-silicon debug, silicon bring-up, and failure analysis

Required qualifications

• 10+ years of hands-on ASIC DFT experience
• Strong knowledge of scan, ATPG, MBIST, LBIST, JTAG, and boundary scan
• Experience with Synopsys, Cadence, or Siemens EDA tools
• Understanding of RTL, synthesis, LEC, STA, and physical design flows
• Strong debugging and root cause analysis skills