Lead DFT Engineer

Job Summary

As the Design for Test (DFT) Lead, this full-time remote position will architect testing strategies for data center chips, ensuring manufacturability and reliability for edge deployment while overseeing DFT architecture and collaborating with cross-functional teams.

Key Responsibilities:

• Define and implement end-to-end DFT architecture for complex SoCs, including Hierarchical DFT and Boundary Scan
• Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote environments
• Lead post-silicon validation and debug phases on Automated Test Equipment (ATE) to root-cause silicon failures

Required Qualifications:

• 12+ years of experience in DFT, with at least 2 years in a leadership role and a Bachelor's degree in a related field
• Mastery of industry-standard DFT tools such as Synopsys TestMAX and Cadence Modus
• Deep expertise in MBIST, SCAN, and boundary scan (IEEE 1149.1/6)
• Proven track record with FinFET nodes (7nm, 5nm, or below)
• Experience managing DFT in multi-voltage/power-gated designs for edge efficiency