Package Design Methodology Engineer

Job Summary

To support the development of cutting-edge AI and HPC platform packages, the full-time salaried Package Design Methodology Engineer will design and implement VLSI tools, develop applications for project engineers, and optimize workflows for package designers, with opportunities for remote work available.

Key responsibilities:

• Design and implement VLSI tools for silicon and substrate design
• Develop applications to enhance maintainability and usability for project engineers
• Create and optimize flows/tools for package design analysis and validation throughout production stages

Required qualifications:

• BS in Computer Science, Electrical Engineering, or a related field, with 5+ years of experience in flow and methodology development for package design
• Proficiency in Python and/or C++, with strong programming fundamentals
• Experience applying AI/ML techniques in engineering workflows
• Solid understanding of electrical engineering fundamentals relevant to VLSI package design
• Familiarity with VLSI package design, interposer, and IC physical design is a plus