Principal ASIC Design Engineer

Job Summary

Seeking a full-time remote Principal ASIC Design Engineer, the ideal candidate will implement RTL designs for high-speed data paths, collaborate with verification teams on test plans, and define timing constraints while optimizing for performance and power in advanced networking solutions.

Key Responsibilities:

• Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic
• Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues

Required Qualifications:

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field
• 8+ years of post-college experience in digital design with proficiency in Verilog and System Verilog
• Experience in RTL design for high-speed data paths or packet processing in ASICs
• Deep understanding of Host Ethernet adaptor architectures
• Familiarity with timing closure and modern physical design methodologies