Principal ASIC Engineer

Job Summary

Seeking a Principal ASIC Engineer for a remote, full-time position to own synthesis, timing convergence, implementation readiness, and logical design quality across AI accelerator projects, while collaborating with cross-functional teams to drive high-quality RTL into implementation-ready netlists.

Key Responsibilities

• Define and manage synthesis methodology and establish signoff criteria for ASIC generations
• Lead hands-on synthesis using EDA tools and develop SDC constraints for optimal design quality
• Drive logical timing closure and collaborate with teams to mitigate timing risks before implementation

Required Qualifications

• 12+ years of ASIC implementation experience with successful tapeouts
• Expertise in synthesis methodology and timing closure for complex designs
• Proficient in Cadence Genus and/or Synopsys Design Compiler
• Strong SDC expertise and experience with advanced process nodes at 5nm and below
• Hands-on scripting ability in Tcl and Python for automation and flow development