Principal ASIC Physical Design Engineer

Job Summary

Leading the implementation of complex SoCs for next-generation satellite systems, the remote Principal ASIC Physical Design Engineer will manage the full physical design flow from RTL handoff to GDSII, collaborate with various teams, and ensure successful silicon outcomes using advanced FinFET technologies.

Key responsibilities

• Own the complete RTL-to-GDSII flow, including synthesis, floorplanning, and sign-off
• Develop and maintain physical design methodologies to optimize performance, power, and area (PPA)
• Manage and guide external physical design partners, ensuring alignment on milestones and quality standards

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC physical design for high-performance SoCs
• Proven expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens)
• Strong hands-on experience with timing closure and IR drop analysis
• Deep understanding of physical design constraints for multi-clock and multi-voltage SoCs