Principal ASIC Verification Engineer

Job Summary

Seeking a Principal ASIC Design Verification Engineer for a full-time remote position, responsible for verifying the functionality and performance of custom silicon designs while defining verification approaches and collaborating with cross-functional teams.

Key responsibilities

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments
• Build SystemVerilog/UVM test benches and drive testing strategies to validate functionality and corner cases
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations

Required qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC/SoC verification
• Solid understanding of SystemVerilog, digital logic, and hardware design and verification flows
• Proficiency with simulation tools and scripting languages such as Python, Perl, or TCL
• Experience with test planning, UVM-based testbench development, and functional coverage