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Principal Design Engineer

Location: Remote
Compensation: Salary
Reviewed: Wed, Aug 05, 2026
This job expires in: 14 days

Job Summary

Seeking a Principal Design Engineer for a fully remote, direct hire position who will lead the design and development of advanced RTL-based IP solutions for complex ASIC and SoC applications, emphasizing innovation and technical ownership.

Key responsibilities
  • Lead the architecture, design, and development of advanced RTL-based IP solutions
  • Design and implement high-quality RTL using Verilog and/or SystemVerilog, focusing on maintainability and performance
  • Collaborate with cross-functional teams to support successful IP integration and resolve technical challenges
Required qualifications
  • 8+ years of experience in designing RTL for ASIC, SoC, or complex digital IP development
  • Strong expertise with Verilog and/or SystemVerilog for complex digital design
  • Hands-on experience with DisplayPort, Display Stream Compression (DSC), or similar technologies
  • Proven success in delivering high-quality digital designs from architecture through implementation
  • Experience with block-level and system-level verification methodologies and tools

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