Principal Engineer, NOC Architecture

Job Summary

Leading the definition and evolution of next-generation Network-on-Chip (NOC) and DDR memory controller architecture for complex SoCs, the full-time Principal Engineer, NOC Architecture will manage architectural design, performance optimization, and cross-functional collaboration to ensure robust and production-ready systems.

Key responsibilities

• Define end-to-end architecture for NOC and DDR memory controller subsystems in advanced SoCs
• Drive architectural tradeoffs across bandwidth, latency, QoS, and reliability for memory subsystems
• Lead performance modeling and analysis to evaluate workload behavior and system performance optimization

Required qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field
• 12+ years of experience in SoC or ASIC architecture with significant ownership of interconnect and memory subsystem design
• Deep expertise in NOC architecture and DDR memory controller architecture
• Strong understanding of high-performance SoC design tradeoffs across performance, power, area, and scalability
• Proven track record of leading cross-functional technical efforts from concept through silicon