Principal Physical Design Engineer

Job Summary

To support a growing physical design team, the full-time Principal Physical Design Engineer will own complex physical implementation tasks, drive critical blocks and top-level integration, and establish methodologies to meet performance, power, area, and schedule targets in a remote work environment.

Key Responsibilities:

• Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff
• Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability
• Drive physical signoff, including DRC, LVS, antenna, density, connectivity, and related physical verification requirements

Required Qualifications:

• 10+ years of ASIC or SoC physical design experience with multiple successful tapeouts
• Expert-level understanding of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification
• Strong expertise in static timing analysis and multi-mode, multi-corner timing closure
• Demonstrated ability to independently own complex blocks or major portions of a chip through signoff
• Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools