Job Summary
An engineering solutions company is in need of a Remote Senior Low Power Design Verification Engineer.
Individual must be able to fulfill the following responsibilities:
- Drive the Design Verification with a focus on Low Power Design Verification
- Develop test plans, create environments and implement scoreboards and checkers
- Resolve issues and bugs
Must meet the following requirements for consideration:
- 7+ years of proven experience as a DV engineer
- Hands-on experience in Coverage Driven verification
- Hands on experience with SystemVerilog and UVM
- Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive simulators
- In depth experience with UPF based simulation flows
- 2+ Years of experience with C/C++
