Senior ASIC Design Engineering Manager

Job Summary

Leading the RTL design engineering team, the full-time Senior ASIC Design Engineering Manager will oversee the development of high-performance networking ASICs, manage delivery schedules, and drive organizational strategy in a remote environment.

Key Responsibilities

• Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans
• Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track
• Lead long-term headcount planning and organizational design for the ASIC department, identifying skill gaps and executing global talent acquisition strategies

Required Qualifications

• 15+ years in the semiconductor industry, with at least 5 years in people management
• B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience
• Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams
• Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment
• Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), and verification methodologies