Senior ASIC Design Verification Engineer

Job Summary

Seeking a Senior ASIC Design Verification Engineer for a remote, full-time position responsible for verifying custom silicon designs, developing verification plans, and collaborating with cross-functional teams to ensure robust performance and functionality.

Key responsibilities

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments, building SystemVerilog/UVM test benches
• Drive constrained-random and directed testing strategies, run simulations, triage failures, and collaborate with RTL designers to resolve issues
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and participate in design reviews to influence design-for-verification best practices

Required qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 5+ years of experience in ASIC/SoC verification
• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows
• Proficiency with simulation tools, waveform debug, coverage tools, and scripting languages (e.g., Python, Perl, TCL)
• Experience with test planning, UVM-based testbench development, and regression management