Senior ASIC Engineer

Job Summary

To advance AI technology, the full-time Senior LPU ASIC Engineer will be responsible for full-flow ownership of chip design, cross-functional optimization with various teams, and leading tapeout execution while working remotely.

Key responsibilities

• Manage full-flow ownership including synthesis, floorplanning, and timing constraints at both block and top levels
• Collaborate with IP, Front-End logic design, and Architecture teams to optimize power, performance, and area (PPA) in chip design
• Lead design closure and ensure compliance for successful GDSII handoff and tapeout

Required qualifications

• B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred) with 5+ years in full-flow physical design for large-scale SoCs
• Proven track record of driving designs through the complete RTL-to-GDSII flow
• Deep understanding of low-power design intent and formal equivalency checks
• Expertise in advanced clock tree synthesis and sign-off timing analysis
• Skilled in scripting (TCL, Python, Perl) for automation and integration of AI-driven optimizations