Senior ASIC Engineer

Job Summary

To support a critical silicon engineering program, the full-time remote Senior ASIC DFT / CDC Constraints Engineer will lead Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) methodology, design robust RTL with CDC/RDC considerations, and improve verification workflows.

Key responsibilities

• Lead CDC and RDC methodology for silicon chips
• Design and implement robust RTL with CDC/RDC considerations
• Define and improve CDC/RDC check flows in collaboration with CAD teams

Required qualifications

• 10+ years in ASIC chip design / RTL development
• Strong expertise in CDC / RDC concepts and implementation
• Experience with DFT methodologies and constraints
• Strong knowledge of Static Timing Analysis (STA)
• Experience with SystemVerilog Assertions (SVA) and VCS simulation