Senior ASIC Engineer

Job Summary

Owning synthesis and timing convergence, the hybrid Senior Mid-End ASIC Engineer will be responsible for transforming high-quality RTL into implementation-ready netlists while collaborating closely with architecture and backend implementation teams.

Key Responsibilities

• Define and manage synthesis methodology for ASIC generations, ensuring scalable flows and establishing signoff criteria
• Lead hands-on synthesis using EDA tools, developing and maintaining SDC constraints and driving continuous improvement of synthesis QoR
• Oversee logical timing closure, performing root-cause analysis of timing bottlenecks and collaborating with cross-functional teams to mitigate risks

Required Qualifications

• 12+ years of ASIC implementation experience with multiple successful tapeouts
• Expert-level proficiency in synthesis methodology and flow development
• Deep expertise in timing closure for complex, multi-million-gate designs
• Strong command of Cadence Genus and/or Synopsys Design Compiler
• Hands-on experience with advanced process nodes at 5nm and below