Senior ASIC Physical Design Engineer

Job Summary

Working remotely, the full-time Senior ASIC Physical Design Engineer will implement advanced SoCs for next-generation satellite systems, contributing to the complete physical design flow from synthesis to GDSII while collaborating with cross-functional teams to achieve timing closure and optimize performance, power, and area (PPA).

Key responsibilities

• Execute the complete physical design flow for complex SoC blocks, including synthesis, floorplanning, place & route, and physical verification
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools
• Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 5-10 years of experience in ASIC physical design for complex SoCs
• Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent)
• Strong understanding of timing analysis, power optimization, and physical verification flows
• Familiarity with FinFET technologies and hierarchical or flat SoC design methodologies