Senior ASIC Verification Engineer

Job Summary

A company is looking for a Senior ASIC Verification Engineer.

Key Responsibilities:

• Participate in the development of UVM environments to verify RTL at various levels
• Develop and execute functional tests according to verification test plans
• Collaborate with cross-functional teams to ensure high design quality

Minimum Qualifications:

• 10+ years of experience in writing code using System Verilog Language
• Experience with verification for complex SoCs using VCS or equivalent simulation tools
• Proficiency in debugging fails to the line of RTL using Verdi or equivalent tools
• Experience in ground-up testbench development
• B. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering