Senior Formal Verification Engineer

Job Summary

A company is looking for a Senior Formal Verification Engineer to verify ASICs using formal verification tools.

Key Responsibilities

• Verify AI-related ASIC designs and features using formal verification methods
• Collaborate with architecture and RTL teams to specify properties and resolve design issues
• Develop and implement advanced formal verification methodologies and environments for complex ASIC designs

Required Qualifications

• BS/MS/PhD or equivalent experience in Computer Science, Computer Engineering, or Electrical Engineering
• 12+ years of experience in ASIC verification, with 8+ years focused on formal verification methods
• Mastery of SystemVerilog Assertions (SVA) and formal property verification
• Proficient in at least one popular formal verification tool (e.g., JasperGold, VC Formal)
• Good scripting skills for flow automation (e.g., Tcl, Python)