Senior Formal Verification Engineer

Job Summary

A company is looking for a Senior Formal Verification Engineer.

Key Responsibilities

• Verifying AI-related sophisticated ASIC builds and features using advanced formal verification methods
• Collaborating with architecture and RTL teams to specify properties and resolve complex issues
• Developing advanced formal verification environments and methodologies for complex ASIC designs

Required Qualifications

• BS/MS/PhD or equivalent experience in Computer Science, Computer Engineering, or Electrical Engineering
• 5+ years in ASIC verification with 3+ years focused on formal verification methods
• Proficiency in SystemVerilog Assertions (SVA) and formal property verification
• Experience with at least one popular formal verification tool in the industry
• Strong skills in applying AI tools in engineering work