Senior Mixed-Signal Verification Engineer

Job Summary

Owning the creation of behavioral modeling, the full-time remote Senior Mixed-Signal Verification Engineer will drive mixed-signal verification methodology and collaborate with design teams to develop state-of-the-art mixed-signal SoCs for advanced satellite applications.

Key responsibilities

• Develop high-level behavioral models for analog and mixed-signal IP components
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification

Required qualifications

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field
• 5+ years of experience in analog/mixed-signal modeling and/or AMS verification
• Hands-on experience with SystemVerilog, Verilog-AMS, or equivalent modeling languages
• Strong understanding of analog/mixed-signal circuits such as PLLs, LDOs, and ADC/DACs
• Experience with mixed-signal co-simulation environments like Cadence AMS Designer or Synopsys VCS AMS