Senior SRAM Layout Engineer

Job Summary

Seeking a hands-on Senior SRAM Layout Engineer, the full-time position will lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes, managing the complete custom layout process from initial floorplanning through DRC/LVS-clean tapeout while collaborating with various teams.

Key responsibilities:

• Manage the custom layout process for SRAM bitcell arrays and memory macros in advanced CMOS technologies
• Develop and improve floorplans, ensuring power grid design and routing channels meet specifications
• Collaborate with circuit designers and integration teams to resolve layout and verification issues

Required qualifications:

• BSEE or equivalent experience
• 10+ years of custom IC layout experience, with at least 5 years in SRAM or memory IP layout
• Hands-on experience with advanced CMOS technology, particularly FinFET or GAA nodes
• Extensive experience in Cadence Virtuoso and DRC/LVS debugging using tools like Calibre
• Solid understanding of SRAM and memory layout principles and advanced-node layout limitations