Senior Staff Virtual Platform Engineer

Job Summary

Specializing in virtual platforms, the full-time Senior Staff Virtual Platform Engineer will develop high-level system virtual models of complex SoC hardware using SystemC TLM and QEMU, collaborating with cross-functional teams to ensure accurate representation of architectures.

Key responsibilities

• Design and develop SystemC TLM models to represent SoC architectures accurately
• Integrate various components into the SystemC simulator, including processors and custom IP blocks
• Collaborate with hardware designers and software engineers to translate system requirements into detailed models

Required qualifications

• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field with 6+ years of relevant experience, or a Master's degree with 5+ years, or a PhD with 4+ years
• 3+ years of experience with programming languages such as C, C++, Java, or Python
• Extensive knowledge of SystemC TLM or QEMU
• Experience in designing and implementing complex SoC TLM models
• Strong background in C++ programming for effective model development