Senior Verification Engineer

Job Summary

A company is looking for a Senior Verification Engineer.

Key Responsibilities

• Develop verification and simulation strategies, and conduct design reviews
• Construct and maintain simulation environments using System Verilog with UVM
• Lead a team of verification engineers to fully verify complex devices

Required Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science; Master's degree preferred
• Minimum of 10 years of verification engineering experience required
• Experience with simulation tools such as Mentor Graphics Modelsim/Questasim
• Capability to analyze Verilog RTL and diagnose test failures
• US Citizenship is required