Senior VLSI Engineer

Job Summary

Driving the complete logic synthesis process, the hybrid/remote Senior VLSI Engineer will take end-to-end ownership of synthesis and quality signoff for key blocks and sub-chips while collaborating closely with RTL design engineers to optimize netlist delivery.

Key Responsibilities

• Drive and own the complete logic synthesis process for designated blocks and sub-chips, ensuring optimal area, power, and performance metrics
• Define, execute, and monitor rigorous sanity checks to achieve high-quality Synthesis Signoff
• Provide actionable RTL coding guidelines and structural recommendations to optimize designs for synthesis

Required Qualifications

• 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis
• Hands-on experience with industry-standard synthesis tools, particularly Cadence Genus, and STA signoff tools like Tempus or PrimeTime
• Strong foundational knowledge of STA, timing constraints, and multi-mode multi-corner analysis
• Deep understanding of Verilog/SystemVerilog and digital logic design
• Proficiency in Tcl, Python, or Perl for automation and reporting scripts