Silicon Validation Engineer

Job Summary

A company is looking for a Silicon Validation Engineer 4.

Key Responsibilities

• Develop scripts to extract metrics from Vivado implementation runs
• Automate collection of timing, utilization, and quality metrics using TCL and Python
• Integrate extracted metrics into existing data pipelines and tooling

Required Qualifications

• 8-10 years of experience in FPGA implementation flows
• Strong experience with TCL scripting for Vivado
• Proficiency in Python
• Solid understanding of timing and utilization metrics
• Ability to support and modify FPGA constraint and automation scripts