Silicon Verification Engineer

Job Summary

A company is looking for a Verification Engineer for a 4-month contract position.

Key Responsibilities

• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes

Required Qualifications

• Minimum 2+ years experience with SystemVerilog and UVM
• Minimum 2+ years experience with Mixed Signal Verification
• Minimum 2+ years experience with Design Verification Methodology
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related degree is preferred
• 2-4 years of relevant experience required