Silicon Verification Engineer

Job Summary

A company is looking for a Silicon Verification Engineer 2.

Key Responsibilities:

• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and develop tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures, and support post-silicon verification activities

Required Qualifications:

• Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or related degree preferred
• 2-4 years of relevant experience required
• Minimum 2+ years' experience with System Verilog and UVM
• Minimum 2+ years' experience with Mixed Signal Verification
• Minimum 2+ years' experience with Design Verification Methodology