Silicon Verification Engineer

Job Summary

A company is looking for a Silicon Verification Engineer 2 to join their verification team supporting advanced chip development.

Key Responsibilities

• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and develop tests, test generators, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures, and support post-silicon verification activities

Required Qualifications

• 2+ years experience with SystemVerilog and UVM
• 2+ years experience with Mixed Signal Verification
• 2+ years experience with Design Verification Methodology
• Strong grasp of verification methodologies such as VMM/OVM/UVM
• Experience in pre and post silicon verification test flow and automated test benches