Silicon Verification Engineer

Job Summary

A company is looking for a Silicon Verification Engineer (contract).

Key Responsibilities

• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes

Required Qualifications

• 2-4 years of relevant experience required
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree preferred
• Proficient in using Verilog and VMM/OVM/UVM
• Experience in pre and post silicon verification test flow and automated test benches