STA Lead Physical Design Engineer

Job Summary

A company is looking for a STA Lead, Physical Design Engineer.

Key Responsibilities:

• Conduct full chip timing analysis from early investigation to final implementation and tape out
• Develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure
• Collaborate with architects and logic designers to generate timing constraints and partner with physical design teams for design sign-off

Required Qualifications:

• PhD, Masters or Bachelors Degree in Electrical Engineering, Electrical Engineering and Computer Science, or Computer Science
• Hands-on experience in ASIC timing constraints generation and timing closure
• Expertise in industry standard timing EDA tools such as Prime Time and StarRC
• Deep understanding of timing closure in various functional and test modes, particularly in deep-sub micron processes
• Proficient in scripting languages such as TCL, Perl, Python, and csh/bash