Job Summary

A software company is filling a position for a Telecommute Senior Design Verification Engineer in Fremont.

Core Responsibilities of this position include:

• Architecting and building SV/UVM based Verification environments
• Accelerating processing of location data
• Developing full Verification plans and tests

Required Skills:

• Bachelor's, Electrical Engineering
• 5+ years of experience verifying complex, custom ASICs
• Experience with modern SystemVerilog / UVM based Verification environments
• Experience with the full Verification flow from Unit / IP to “Full-chip” / SOC level