ASIC Design Engineer

Job Summary

Working remotely, the full-time ASIC Design Engineer will design, implement, and deliver IP blocks and subsystems for inference ASICs/SoCs, collaborating closely with senior engineers and cross-functional teams while gaining hands-on experience with high-performance silicon.

Key Responsibilities

• Implement SystemVerilog RTL for assigned blocks based on microarchitecture specifications and contribute to documentation
• Run and debug lint, CDC/RDC, and synthesis checks, resolving issues and assisting with timing analysis
• Support integration of standard interfaces and IP, while writing and maintaining scripts to enhance design flows

Required Qualifications

• BS/MS in Electrical Engineering/Computer Engineering or related field with 0-3 years of ASIC/SoC RTL design experience
• Solid knowledge of SystemVerilog/Verilog for synthesizable RTL design
• Understanding of digital design fundamentals including clocking, resets, and pipelining
• Exposure to front-end tools and flows from industry or academic projects
• Familiarity with standard interfaces such as AMBA AXI, DDR, or PCIe