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Design for Test Engineer
Job Summary
A company is looking for a Design for Test Engineer - RISC-V - Contractor.
Responsibilities:
- Implement DFT features into RTL using Verilog
- Develop and optimize DFT architectures and micro-architectures
- Perform ATPG and test coverage analysis using industry-standard tools
Experience & Qualifications:
- BS/MS/PhD in EE, ECE, CE, or CS with 5+ years of industry experience in advanced DFx techniques
- Hands-on experience implementing DFx in finFET technologies
- Proficiency in industry-standard ATPG and DFx insertion CAD tools
- Familiarity with SystemVerilog and UVM
- Strong RTL coding skills for DFx logic, including lock-up latches, clock gates, and scan anchors
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COMPLETE JOB DESCRIPTION
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