Design Verification Manager

Job Summary

Leading a verification team in a hybrid work environment, the full-time Design Verification Manager will develop and implement verification plans for mixed-signal integrated circuits while mentoring engineers and collaborating with cross-functional teams.

Key responsibilities:

• Lead and mentor a geographically distributed team of verification engineers, managing deliverables and project schedules
• Define and implement comprehensive verification strategies and test plans for digital/mixed-signal designs, ensuring coverage closure and generating technical documentation
• Manage the design and implementation of complex testbenches using SystemVerilog and UVM, while improving verification scalability and automation

Required qualifications:

• 10+ years of industry experience in integrated circuit design verification
• B.S. or M.S. in Electrical or Computer Engineering
• Experience leading and mentoring engineers or projects
• Proficiency in SystemVerilog, UVM, Verilog/VHDL, and EDA verification tools
• In-depth knowledge of digital integrated circuit verification with MCU-based hardware systems