Formal Verification Engineer

Job Summary

Seeking a Formal Verification Engineer to work remotely, the successful candidate will utilize formal methods to ensure the correctness of high-performance RISC-V CPUs and AI compute platforms, collaborating closely with architects and RTL designers to develop verification environments and analyze failures.

Key Responsibilities

• Develop properties and build formal verification environments to prove complex hardware behavior
• Analyze failures and drive issues to closure, ensuring design correctness
• Collaborate with CPU architects and RTL designers to improve design quality and uncover corner cases

Required Qualifications

• 6+ years of experience in design verification, formal verification, or related RTL verification for CPUs, SoCs, or complex digital designs
• Hands-on experience with formal verification methodologies and tools, including property checking and assertions
• Strong SystemVerilog skills, with experience in writing and debugging SVA
• Solid understanding of digital design and computer architecture, particularly with CPU pipelines and control logic
• Strong programming and scripting skills in Python, Tcl, C/C++, or similar