Front End Design Verification Engineer

Job Summary

To contribute to the verification of the fetch unit for next-generation high-performance RISC-V CPU cores, the Front End Design Verification Engineer will work remotely, collaborating with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, and debug complex failures.

Key responsibilities

• Develop and implement verification strategies for the fetch unit, ensuring correct instruction handling across various workloads
• Create and execute sophisticated tests to identify and debug complex failures in the CPU front-end logic
• Collaborate with cross-functional teams, including architects and RTL designers, to enhance the performance and correctness of the CPU design

Required qualifications

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or complex digital designs
• Strong expertise in SystemVerilog and UVM, including constrained-random testing and assertions
• Solid understanding of CPU architecture, particularly in instruction fetch, decode, and branch prediction
• Experience debugging RTL and simulation failures using standard tools and waveforms
• Proficiency in programming languages such as C/C++ and/or Python for effective collaboration across teams