Principal ASIC Design Engineer

Job Summary

Leading the implementation of complex SoCs for next-generation satellite systems, the remote Principal ASIC Physical Design Engineer will manage the full physical design flow from RTL handoff to GDSII while collaborating with cross-functional teams and external partners to ensure first-pass silicon success.

Key Responsibilities

• Own the complete RTL-to-GDSII flow, including synthesis, floorplanning, place & route, and sign-off
• Develop and maintain physical design methodologies and automation to optimize performance, power, and area (PPA)
• Collaborate with front-end and verification teams to ensure clean handoffs and efficient design iterations

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC physical design for high-performance SoCs
• Proven expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens)
• Strong hands-on experience with timing closure and ECO implementation
• Experience managing or coordinating offshore/outsourced physical design teams or vendors