Principal ASIC Engineer

Job Summary

Leading the implementation of complex SoCs for next-generation satellite systems, the remote Principal ASIC Synthesis and Timing Engineer will manage the RTL-to-Synthesis flow, develop design methodologies, and collaborate with cross-functional teams to ensure timing closure and successful silicon outcomes.

Key responsibilities

• Own the complete RTL-to-Synthesis flow, integrating floorplanning information for physical synthesis
• Develop and maintain design methodologies and automation to optimize performance, power, and area (PPA)
• Manage external physical design partners and ensure alignment on milestones and quality standards

Required qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC design for high-performance SoCs
• Proven expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens)
• Strong hands-on experience with timing closure and low power implementation
• Deep understanding of physical design constraints for multi-clock and multi-voltage SoCs