Senior ASIC Design Engineer

Job Summary

Leading the design and implementation of critical IP blocks for inference ASICs/SoCs, the full-time Senior ASIC Design Engineer will define microarchitecture, deliver SystemVerilog RTL, and mentor junior engineers in a remote work environment.

Key Responsibilities

• Define and document microarchitecture for complex IP blocks/subsystems and deliver production-quality SystemVerilog RTL
• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up while owning PPA metrics for assigned blocks
• Architect and integrate high-performance interconnects and memory interfaces, ensuring seamless collaboration with internal stakeholders

Required Qualifications

• BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon
• Proven track record of leading designs from specification to microarchitecture RTL signoff with strong PPA outcomes
• Deep SystemVerilog RTL expertise, including clocking, resets, and protocol correctness
• Extensive experience with front-end flows/tools using major EDA suites
• Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, and high-throughput datapaths