Senior ASIC Design Verification Engineer

Job Summary

Leading verification efforts for AI inference ASICs, the full-time Senior ASIC Design Verification Engineer will develop and execute advanced verification methodologies, collaborate with cross-functional teams, and manage verification schedules in a hybrid work environment.

Key Responsibilities

• Develop and execute verification strategies for AI inference ASICs
• Define and implement comprehensive test plans and verification methodologies
• Lead the development of verification environments using SystemVerilog UVM

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in ASIC verification
• Expertise in SystemVerilog UVM and simulation tools
• Strong knowledge of verification planning and testbench development
• Experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics)