Senior ASIC Physical Design Engineer

Job Summary

To support the development of next-generation satellite systems, the remote Senior ASIC Physical Design Engineer will implement advanced SoCs, managing the full physical design flow from synthesis to GDSII, while collaborating with cross-functional teams to achieve timing closure and optimize performance.

Key responsibilities

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, and physical verification
• Perform timing closure and optimization using industry-standard tools across multiple corners and modes
• Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 5-10 years of experience in ASIC physical design for complex SoCs
• Hands-on experience with industry-standard tools such as Synopsys ICC2 or Cadence Innovus
• Strong understanding of timing analysis, power optimization, and physical verification flows
• Familiarity with FinFET technologies and hierarchical or flat SoC design methodologies