Senior ASIC Verification Engineer

Job Summary

Leading the DFT and ASIC verification efforts for next-generation coherent optical communications products, the remote Senior ASIC Verification Engineer will implement SSN-based test flow architectures, generate ATPG test patterns, and ensure DFT feasibility through design evaluations.

Key responsibilities

• Implement SSN-based test flow DFT architectures, including scan insertion and memory BIST, using Siemens Tessent tools
• Generate ATPG test patterns and support silicon failure debug and post-silicon validation
• Evaluate design readiness for scan insertion and integrate DFT fabrics within subsystems

Required qualifications

• Bachelor's degree with 8 years, Master's with 6 years, or PhD with 3 years of related experience
• Experience with ASICs, including DFT setup, integration, and validation
• Proven ability in implementing DFT architectures and generating test patterns
• Strong RTL experience for debugging DFT-related issues
• Familiarity with Verilog/SystemVerilog and advanced silicon process nodes