Senior DFT Engineer

Job Summary

Owning the end-to-end DFT implementation, the full-time Senior DFT Engineer will define micro-architecture for accelerators, integrate DFT into RTL and third-party IP, and ensure high-quality silicon bring-up through pre-silicon validation while working remotely.

Key Responsibilities

• Micro-architect and implement DFT instrumentation logic, including scan insertion and memory BIST
• Develop comprehensive DFT verification plans and validate functionality through simulation and gate-level verification
• Collaborate with backend implementation teams to ensure successful physical realization of the DFT architecture

Required Qualifications

• A BS, MS, or PhD in Electrical Engineering or Computer Engineering
• 8+ years of ASIC development experience with hands-on DFT implementation on complex SoCs
• Deep understanding of scan architectures, ATPG, and boundary scan
• Experience with Siemens Tessent DFT solutions
• Strong RTL design skills using Verilog/SystemVerilog